The present invention relates to integrated circuit structures and more particularly to dielectric isolation in such integrated circuit structures, particularly by air-isolation.
The form of most existing integrated circuits is the so-called monolithic form. Such a structure contains great numbers of active and passive devices in a block or monolith of semiconductor material. Electrical connections between these active and passive devices are generally made on a surface of the semiconductor block of material. Until recently, junction isolation has been by far the most widely practiced manner of isolating devices or circuits in the integrated circuit from each other. For example, active P-type diffusions are customarily used to isolate conventional FET and bipolar devices from one another and from other devices such as the resistors and capacitors. Such junction isolation is also used in integrated circuits utilizing field effect transistor devices. More detailed descriptions of junction isolation may be found in U.S. Pat. Nos. 3,319,311; 3,451,866; 3,508,209 and 3,539,876.
Although junction isolation has provided excellent electrical isolation in integrated circuits which have functioned very effectively over the years, at the present stage of the development of the integrated circuit art, there is an increasing demand in the field of digital integrated circuits for faster switching circuits. It has long been recognized that the capacitive effect of the isolating P-N junctions has a slowing effect on the switching speed of the integrated circuits. Until recently, the switching demands of the integrated circuits have been of a sufficiently low frequency that the capacitive effect in junction isolation has presented no major problems. However, with the higher frequency switching demand which can be expected in the field in the future, the capacitive effect produced by junction isolation may be an increasing problem. In addition, junction isolation requires relatively large spacing between devices, and, thus, relatively low device densities which is contrary to higher device densities required in large scale integration. Junction isolation also tends to give rise to parasitic transistor effects between the isolation region and its two abutting regions. Consequently, in recent years there has been a revival of interest in integrated circuits having dielectric isolation instead of junction isolation. In such dielectrically isolated circuits, the semiconductor devices are isolated from each other by insulative dielectric materials or by air.
Conventionally, such dielectric isolation in integrated circuits has been formed by etching channels in a semiconductor member corresponding to the isolation regions from the back side of the member, i.e., the side opposite to the planar surface at which the devices and wiring of the integrated circuit are to be formed. This leaves an irregular or channeled surface over which a substrate back side, usually a composite of a thin dielectric layer forming the interface with the semiconductor member covered by a thicker layer of polycrystalline silicon is deposited. Alternatively, the polycrystalline silicon need not be deposited in which case, the channels would provide air-isolation. Next, the other or planar surface of the semiconductor member may be either mechanically ground down or chemically etched until the bottom portions of the previously etched channels are reached. This leaves the structure wherein a plurality of pockets of semiconductor material surrounded by a thin dielectric layer are either supported on a polycrystalline silicone substrate and separated from each other by the extensions of the polycrystalline substrate or in the absence of the polysilicon, a structure in which the pockets of semiconductor material are, in effect, "air-isolated" from each other. While such structures provide an essentially flat and thus wirable planar surface of coplanar pockets of semiconductor material, such integrated circuit structures have limited utility with integrated circuits of high device densities. This is due to the fact that the etched channels which correspond to the isolation regions must be formed from the back side of the integrated circuit substrate and etched until the level of the active planar surface of the substrate is reached.
It is recognized in the art that when etching from the back side of an integrated circuit member the etching must be made to greater depth than when etching directly from the planar front surface in order to insure uniform lateral isolation. It is also recognized that when etching through a member, the extent of lateral etching will be substantially the same as the depth of etching. Accordingly, when etching channels from the back side of the substrate, so much lateral "real estate" is consumed on the wafer that such an approach has very limited practicality in high density integrated circuits.
On the other hand, if the etching to form the channels in the above dielectric isolation or air-isolation structure is carried out from the active or front surface of the integrated circuit, only limited lateral etching is necessary to reach practical isolation depths. However, the result is an essentially corrugated active surface rather than a planar one. Such a corrugated active surface is, of course, difficult to wire, i.e., form integrated circuit metallurgy interconnections by conventional photolithographic integrated circuit fabrication techniques.
Another approach which has been utilized for forming lateral dielectric isolation in the art involves the formation of recessed silicon dioxide lateral isolation regions, usually in the epitaxial layer where the semiconductor devices are to be formed, through the expedient of first selectively etching a pattern of recesses in the layer of silicon, and then thermally oxidizing the silicon in the recesses with appropriate oxidation blocking masks, e.g., silicon nitride masks, to form recessed or inset regions of silicon dioxide which provide the lateral electrical isolation. Representative of the prior art teaching in this area are U.S. Pat. No. 3,648,125 and an article entitled, "Locos Devices", E. Kooi et al, Philips Research Report 26, pp. 166-180 (1971).
While this approach has provided both planarity at the active device integrated circuit surface as well as good lateral dielectric isolation, it has encountered some problems. Originally, the art applied the silicon nitride masks directly onto the silicon substrates. This gave rise to problems associated with high stresses created on the underlying silicon substrate by the silicon nitride-silicon interface. Such stresses were found in many cases to produce dislocations in the silicon substrate which appear to result in undesirable leakage current pipes and otherwise adversely affect the electrical characteristics of the interface. In order to minimize such interface stresses with silicon nitride layers, it has become the practice in the art to form a thin layer of silicon dioxide between the silicon substrate and the silicon nitride layer. During such thermal oxidation, there is a substantial additional lateral penetration of silicon oxide from the thermal oxidation beneath the silicon nitride. This lateral penetration is greatest at the mask-substrate interface to provide a laterally sloping structure known and recognized in the prior art as the undesirable "bird's beak".
The publications, "Local Oxidation of Silicon; New Technological Aspects", by J. A. Appels et al, Philips Research Report 26, pp. 157-165, June 1971, and "Selective Oxidation of Silicon and its Device Application", E. Kooi et al, Semiconductor Silicon 1973, published by the Electrochemical Society, Edited by H. R. Huff and R. R. Burgess, pp. 860-879, are representative of the recognition in the prior art of the "bird's beak" problems associated with silicon dioxide-silicon nitride composite masks, particularly when used in the formation of recessed silicon dioxide by thermal oxidation. Because of such "bird's beak" problems, the art has experienced some difficulty in achieving well-defined lateral isolation boundaries.
In addition, while, as previously mentioned, air isolation has been used in the prior art in integrated circuits, no practical approach has been developed for the application of air isolation to high density, large scale integrated circuits.